The present invention relates to a memory cell structure, and more particularly to a flash memory cell structure which has a high-density (on the order of about 2F2) associated therewith.
From a circuit aspect, there are two major types of flash memory, i.e., NAND and NOR type. From a device structure aspect, there are many different kinds of flash memory, the most popular structures are the stack gate and split gate. The stack gate device has its entire channel region covered by a floating gate overlapped by a control gate. The split gate device, on the other hand, has part of its channel controlled directly by the floating gate which is modulated by the control gate. There are many other kinds of flash memory, such as virtual ground flash array, and other kinds of split gate NVRAM (non-volatile random access memory) having both control and select gates. Each type of flash memory device has its own advantages and disadvantages associated therewith.
A conventional high-density, high-speed NOR type NVRAM in general has a random read access speed of about 30 nanoseconds, program (or write) speed of from about 1 microsecond to about 10 microseconds, write/erase endurance of about 1E6 cycles, as well as data holding time for greater than 10 years and a cell size of about 0.5 xcexcm2.
The most common programming mode is channel hot electron (CHE) injection programming. During write, the control gate is biased to a high voltage level (of from about 7 to about 9 V), while the source is maintained at ground, and the drain is biased to about 3 to about 5 V. Hot electrons generated in the channel region will be injected into the floating gate causing the threshold voltage of the device to shift. For an nMOS flash memory device, the gate oxide has a thickness of from about 7 to about 12 nm, and the channel length is about 0.25 to about 0.5 xcexcm.
Another programming mode is called Fowler Nordhein (FN) tunneling programming. In this case, a relatively high control gate voltage (about 12 to about 20 V) is needed, while both drain and source can be tied to ground. Such a high programming voltage is needed because the electric field, Eox, which allows tunneling, is about 12 MV/cm. Electrons from the inversion layer in the channel area will tunnel into the floating gate. The advantage of this prior art scheme, however, is low programming power. The most common erase operation is to apply a high voltage of about 12 V on the source side to trigger source side erasure. During the erase operation, the substrate is grounded and the drain side is floating. It is also possible to adopt FN tunneling to the erase operation by applying a negative voltage to the gate (e.g., xe2x88x928 to xe2x88x929 V) and a positive voltage (e.g., 3 to 5 V) to the drain and let the source float.
In general, the size of flash memory cells can be made smaller than that of a DRAM (dynamic random access memory). A high-density flash memory contains only-one transistor with a floating gate. Normally, a NAND type array has higher density than NOR type array. However, the performance of NAND type flash memory is not as good as the NOR type. This occurs since programming and reading one cell in the wordline sometimes requires rippling through many cells in a row.
In view of the above drawbacks with prior art flash memory cells, there is a need for forming a new flash memory cell structure which achieves an ultra-high packing density.
One object of the present invention is to provide a NVRAM-flash memory cell structure which achieves an ultra-high packing density that is on the order of about 2F2 where F is the minimum feature size.
Another object of the present invention is to provide a NVRAM flash memory cell structure that allows two cells to be formed adjacently inside a trench such that the two cells can be used to store two bits of data, or one bit of data with complementary values.
A further object of the present invention is to provide a NVRAM flash memory cell structure comprising at least an xe2x80x9cL-shapedxe2x80x9d floating gate wherein only one side of the L-shaped floating gate overlaps a source line.
A still further object of the present invention is to provide a flash memory cell structure wherein the source line (i.e., program line) of the cell can be separately controlled during reading and programming. This object of the present invention is unlike that of conventional flash memory cells wherein a common source terminal is employed. This feature of the inventive flash memory cell structure enables twin-cells as well as two-bit operation.
An even further object of the present invention is to provide a method of forming a high-density and high-performance flash memory cell.
These and other objects and advantages are achieved in the present invention by providing a flash memory cell structure which includes L-shaped floating gates in trenches that are formed in a Si-containing semiconductor substrate, where one side (bottom) of the floating gate overlaps a source/drain diffusion. This allows two pairs of vertically stacked MOSFETs (i.e., floating gate and the control gate) to be formed in each trench enabling source side programming and 2 bits/trenches (each bit occupying 2F2 in area). Alternatively, one bit can be stored if greatly increased noise margin, due to differential operation, is required. Another key feature of the inventive flash memory cell structure is a single source line diffusion which is present in the bottom of each trench.
Specifically, the inventive NVRAM flash memory cell structure comprises: a Si-containing substrate having a plurality of trenches formed therein, each trench having sidewalls that extend to a bottom wall, a length and individual segments that include two memory cell elements per segment, each memory cell element comprising (i) a floating gate region having L-shaped gates formed on a portion of each trench sidewall; (ii) a program line overlapping one side of said L-shaped gates present at said bottom wall of each trench and extending along said entire length of said plurality of trenches; and (iii) a control gate region overlying said floating gate region, said control gate region including gates formed on portions of said sidewalls of said trenches:, said gates are coupled to said floating gate regions;
bitline diffusion regions formed in said Si-containing semiconductor substrate abutting each trench segment; and
wordlines that lay orthogonal to said trenches, said wordlines being in contact with a top surface of each control gate region.
The present invention also provides a method for forming the above-mentioned flash memory cell structure. Specifically, the inventive method comprises the steps of:
(a) forming a plurality of trench regions in a surface of a Si-containing substrate: each of said trench regions having sidewalls that extend to a bottom wall that are lined with a first gate dielectric, said bottom wall having an extension implant region formed therein;
(b) forming a doped polysilicon layer, and oxide spacers inside each of said trenches on a portion of said first gate dielectric, while leaving a portion of said first gate dielectric formed on said bottom wall exposed;
(c) implanting a program line through said exposed first gate dielectric, said program line overlapping a portion of said extension implant region;
(d) forming a high-density plasma SiN layer on horizontal surfaces including said exposed first gate dielectric and filling each of said trenches with an oxide fill material;
(e) recessing a portion of said oxide fill material, said oxide spacers, said polysilicon layer and said first gate dielectric so as to form a floating gate region in a lower portion of each trench, said floating gate region including at least L-shaped floating gates;
(f) forming a control gate region overlying said floating gate region, said control gate region including at least a control gate polysilicon layer;
(g) forming at least one line-space mask over portions of said control gate polysilicon layer and segmenting trenches that are not protected by said at least one line-space mask; and
(h) removing said line-space mask and forming bitline diffusion regions in said substrate about said plurality of trenches and wordlines above said control gate polysilicon layer which were previously protected by said at least one line-space mask.